Exam
Name___________________________________

TRUE/FALSE.  Write 'T' if the statement is true and 'F' if the statement is false. 

1) 

The values of an analog signal flow smoothly from one to the next. 

1) 

_______ 

2) 

A sinusoidal waveform is an analog signal. 

2) 

_______ 

3) 

Digital data can be processed and transmitted more efficiently and reliably than analog information. 

3) 

_______ 

4) 

The field that comprises both mechanical and electronic components is known as electro-mechanics. 

4) 

_______ 

5) 

The decimal number system uses nine different symbols. 

5) 

_______ 

6) 

The binary number system uses just two symbols. 

6) 

_______ 

7) 

A waveform that repeats itself at fixed intervals is called a periodic waveform. 

7) 

_______ 

8) 

Digital systems respond to voltage levels that change abruptly between two levels (high and low). 

8) 

_______ 

9) 

The amplitude of a digital waveform is the difference in voltage between the LOW and HIGH levels. 

9) 

_______ 

10) 

The clock signal synchronizes the other waveforms in a circuit. 

10) 

______ 

11) 

Clock signals carry pieces of information such as letters and numbers. 

11) 

______ 

12) 

Serial data is sent along a single conductor, one bit at a time. 

12) 

______ 

13) 

Parallel data is sent along a single conductor, one bit at a time. 

13) 

______ 

14) 

When the inputs to a 2-input AND gate are both HIGH, the output is HIGH. 

14) 

______ 

15) 

When either input to a 2-input AND gate is LOW, the output is LOW. 

15) 

______ 

16) 

When either input to a 2-input OR gate is HIGH, the output is HIGH. 

16) 

______ 

17) 

When both inputs to a 2-input OR gate are both LOW, the output is LOW. 

17) 

______ 

18) 

When the input to a logic inverter is HIGH, the output is LOW. 

18) 

______ 

19) 

Encoders and decoders perform opposite conversions. 

19) 

______ 

20) 

A multiplexer converts parallel data to serial data. 

20) 

______ 

21) 

A demultiplexer is sometimes called a mux. 

21) 

______ 

22) 

A flip-flop is a 1-bit storage device. 

22) 

______ 

23) 

The DIP package style has two parallel rows of through-hole pins. 

23) 

______ 

24) 

The PLCC package has J-type leads on all four edges. 

24) 

______ 

25) 

The flat-pack (FP) IC package style is a surface-mount device. 

25) 

______ 

26) 

The FPGA is a fixed-function device. 

26) 

______ 

MULTIPLE CHOICE.  Choose the one alternative that best completes the statement or answers the question. 

27) 

A circuit that converts an analog waveform to a digital signal is commonly called a(n) ________. 

27) 

______ 

A) 

CAD 

B) 

DAC 

C) 

PLD 

D) 

ADC 

28) 

A circuit that converts an digital signal to an analog waveform is commonly called a(n) ________. 

28) 

______ 

A) 

DAC 

B) 

CAD 

C) 

ADC 

D) 

PLD 

29) 

Of the circuits listed, the one that is most likely to be found in a CD player is a(n) ________. 

29) 

______ 

A) 

analog-to-digital converter 

B) 

programmable logic device 

C) 

SPLD 

D) 

digital-to-analog converter 

30) 

On a negative-going pulse, ________. 

30) 

______ 

A) 

HIGH = 0 and LOW = 1 

B) 

LOW = -1 and HIGH = 1 

C) 

HIGH = 0 and LOW = -1 

D) 

HIGH = 1 and LOW = 0 

31) 

On a digital waveform, the transition time from a LOW level to a HIGH level is called ________. 

31) 

______ 

A) 

rise time 

B) 

pulse width 

C) 

period 

D) 

fall time 

Figure 1-1		

32) 

Which edge in Figure 1-1 is the leading edge? 

32) 

______ 

A) 

1 

B) 

2 

C) 

3 

D) 

Both 1 and 3 

33) 

Which edge in Figure 1-1 is the trailing edge? 

33) 

______ 

A) 

1 

B) 

2 

C) 

3 

D) 

Both 1 and 3 

34) 

The time between transition 1 and transition 3 in Figure 1-1 is the ________. 

34) 

______ 

A) 

pulse width 

B) 

amplitude 

C) 

frequency 

D) 

period 

35) 

On a digital waveform, the transition time from a HIGH level to a LOW level is called ________. 

35) 

______ 

A) 

rise time 

B) 

period 

C) 

fall time 

D) 

pulse width 

36) 

The time from one leading edge on a digital waveform to the next is the waveform ________. 

36) 

______ 

A) 

period 

B) 

pulse width 

C) 

fall time 

D) 

rise time 

37) 

A periodic digital waveform ________. 

37) 

______ 

A) 

repeats itself at a fixed interval 

B) 

has both a HIGH and LOW levels 

C) 

has a duty cycle 

D) 

all of the above 

38) 

The transition times for an ideal digital pulse are ________. 

38) 

______ 

A) 

measured between 10% to 90% of the amplitude 

B) 

infinite 

C) 

measured between 0 and 90% of the amplitude 

D) 

zero 

39) 

An oscilloscope display indicates that the period of a digital waveform is 40 μs. What is frequency of this waveform? 

39) 

______ 

A) 

40 MHz 

B) 

2.5 kHz 

C) 

25 kHz 

D) 

The frequency cannot be determined using the information provided. 

40) 

What is the duty cycle of a digital waveform with a pulse width of 10 ms a period of 90 ms? 

40) 

______ 

A) 

11.1% 

B) 

9% 

C) 

90% 

D) 

10% 

41) 

On a positive-going pulse, the leading edge is the ________. 

41) 

______ 

A) 

falling edge 

B) 

negative-going edge 

C) 

positive-going edge 

D) 

HIGH-to-LOW transition 

42) 

The approximate duty cycle for the digital waveform below is ________.

42) 

______ 

A) 

30% 

B) 

80% 

C) 

50% 

D) 

20% 

43) 

On a negative-going pulse, the leading edge is the ________. 

43) 

______ 

A) 

rising edge 

B) 

positive-going edge 

C) 

negative-going edge 

D) 

LOW-to-HIGH transition 

44) 

On a positive-logic pulse, the trailing edge is the ________. 

44) 

______ 

A) 

rising edge 

B) 

LOW-to-HIGH transition 

C) 

positive-going edge 

D) 

falling edge 

45) 

On a negative-logic pulse, the trailing edge is the ________. 

45) 

______ 

A) 

positive-going edge 

B) 

falling edge 

C) 

negative-going edge 

D) 

HIGH-to-LOW transition 

Figure 1-2

46) 

Item (1) of the nonideal pulse in Figure 1-2 represents the waveform ________. 

46) 

______ 

A) 

pulse width 

B) 

transition time 

C) 

period 

D) 

amplitude 

47) 

Item (2) of the nonideal pulse in Figure 1-2 represents the waveform ________. 

47) 

______ 

A) 

amplitude 

B) 

rise time 

C) 

fall time 

D) 

pulse width 

48) 

Item (3) of the nonideal pulse in Figure 1-2 represents the waveform ________. 

48) 

______ 

A) 

amplitude 

B) 

rise time 

C) 

fall time 

D) 

pulse width 

49) 

Item (4) of the nonideal pulse in Figure 1-2 represents the waveform ________. 

49) 

______ 

A) 

amplitude 

B) 

rise time 

C) 

fall time 

D) 

pulse width 

50) 

When data is set along a single conductor, it is referred to as ________. 

50) 

______ 

A) 

simultaneous data 

B) 

serial data 

C) 

parallel data 

D) 

none of these 

Figure 1-3

51) 

The symbol in Figure 1-3(A) represents the ________ function. 

51) 

______ 

A) 

OR 

B) 

AND 

C) 

NOT 

D) 

AND/OR 

52) 

The symbol in Figure 1-3(B) represents the ________ function. 

52) 

______ 

A) 

AND 

B) 

OR 

C) 

NON 

D) 

XOR 

53) 

The symbol in Figure 1-3(C) represents the ________ function. 

53) 

______ 

A) 

XOR 

B) 

NOT 

C) 

OR 

D) 

AND 

54) 

The output from an AND gate is HIGH when ________. 

54) 

______ 

A) 

all inputs are HIGH 

B) 

one input is LOW and the remaining inputs are HIGH 

C) 

one input is HIGH and the remaining inputs are LOW 

D) 

all inputs are LOW 

55) 

The output from an AND gate is LOW ________. 

55) 

______ 

A) 

when at least one input is LOW 

B) 

only when all inputs are HIGH 

C) 

only when all inputs are LOW 

D) 

none of the above 

56) 

The output from an OR gate is HIGH ________. 

56) 

______ 

A) 

when at least one input is HIGH 

B) 

only when all inputs are HIGH 

C) 

only when all inputs are LOW 

D) 

none of the above 

57) 

The output from an OR gate is LOW ________. 

57) 

______ 

A) 

only when all inputs are HIGH 

B) 

whenever any input is HIGH 

C) 

only when all inputs are LOW 

D) 

none of the above 

58) 

Which circuit creates an output that indicates whether or not the input values are equal? 

58) 

______ 

A) 

Comparator 

B) 

Encoder 

C) 

Decoder 

D) 

Multiplexer 

59) 

Which circuit converts information into a specific coded form? 

59) 

______ 

A) 

Comparator 

B) 

Encoder 

C) 

Decoder 

D) 

Multiplexer 

60) 

Which circuit converts coded information into a noncoded form? 

60) 

______ 

A) 

Comparator 

B) 

Encoder 

C) 

Decoder 

D) 

Multiplexer 

61) 

Which circuit converts data from serial form to parallel form? 

61) 

______ 

A) 

Demultiplexer 

B) 

Multiplexer 

C) 

Comparator 

D) 

Encoder 

62) 

Which one of the following is not a binary arithmetic function? 

62) 

______ 

A) 

Multiplexing 

B) 

Addition 

C) 

Division 

D) 

Subtraction 

63) 

Two kinds of data selectors are ________ and ________. 

63) 

______ 

A) 

multiplexers, demultiplexers 

B) 

encoders, decoders 

C) 

adders, subtractors 

D) 

comparators, registers 

64) 

Which one of the circuits listed is made up of flip-flops? 

64) 

______ 

A) 

A comparator 

B) 

A converter 

C) 

A register 

D) 

A multiplexer 

Figure 1-4

65) 

The package style in Figure 1-4(A) is a(n) ________. 

65) 

______ 

A) 

SOIC 

B) 

PLCC 

C) 

LCCC 

D) 

FP 

66) 

The package style in Figure 1-4(B) is a(n) ________. 

66) 

______ 

A) 

SOIC 

B) 

PLCC 

C) 

LCCC 

D) 

FP 

67) 

The package style in Figure 1-4(C) is a(n) ________. 

67) 

______ 

A) 

SOIC 

B) 

PLCC 

C) 

LCCC 

D) 

FP 

68) 

The arrow in the figure below points to pin number ________.

68) 

______ 

A) 

12 

B) 

4 

C) 

5 

D) 

13 

69) 

The arrow in the figure below points to pin ________.

69) 

______ 

A) 

16 

B) 

4 

C) 

5 

D) 

17 

70) 

Which IC package style has no leads? 

70) 

______ 

A) 

PLCC 

B) 

SOIC 

C) 

LCCC 

D) 

All must have leads. 

71) 

Which one of the following is not a surface-mount IC package? 

71) 

______ 

A) 

SOIC 

B) 

PLCC 

C) 

DIP 

D) 

FP 

72) 

The first step in the PLD programming process is ________. 

72) 

______ 

A) 

design entry 

B) 

compilation 

C) 

synthesis 

D) 

download 

73) 

The final step in the PLD programming process is ________. 

73) 

______ 

A) 

design entry 

B) 

compilation 

C) 

synthesis 

D) 

download 

74) 

The netlist is generated during the ________ phase of the PLD programming process. 

74) 

______ 

A) 

design entry 

B) 

compilation 

C) 

synthesis 

D) 

download 

75) 

Which of the following is an example of a mechatronics system? 

75) 

______ 

A) 

A laptop computer	 

B) 

An industrial robot 

C) 

A surgical laser 

D) 

None of the above 

 

1) 

TRUE 

2) 

TRUE 

3) 

TRUE 

4) 

FALSE 

5) 

FALSE 

6) 

TRUE 

7) 

TRUE 

8) 

TRUE 

9) 

TRUE 

10) 

TRUE 

11) 

FALSE 

12) 

TRUE 

13) 

FALSE 

14) 

TRUE 

15) 

TRUE 

16) 

TRUE 

17) 

TRUE 

18) 

TRUE 

19) 

TRUE 

20) 

TRUE 

21) 

FALSE 

22) 

TRUE 

23) 

TRUE 

24) 

TRUE 

25) 

TRUE 

26) 

FALSE 

27) 

D 

28) 

A 

29) 

D 

30) 

A 

31) 

A 

32) 

A 

33) 

C 

34) 

A 

35) 

C 

36) 

A 

37) 

D 

38) 

D 

39) 

C 

40) 

A 

41) 

C 

42) 

D 

43) 

C 

44) 

D 

45) 

A 

46) 

D 

47) 

B 

48) 

D 

49) 

C 

50) 

B 

51) 

B 

52) 

B 

53) 

B 

54) 

A 

55) 

A 

56) 

A 

57) 

C 

58) 

A 

59) 

B 

60) 

C 

61) 

A 

62) 

A 

63) 

A 

64) 

C 

65) 

A 

66) 

B 

67) 

C 

68) 

C 

69) 

D 

70) 

C 

71) 

C 

72) 

A 

73) 

D 

74) 

C 

75) 

B